Обязанности и достижения:
Layout Engineer at Synopsys. Mask layout design of Analog and Mixed Signal ICs, I/O and ST. cell Libraries, Special I/Os in CMOS 0.28um-28nm technology nodes (USB2.0, USB3.0). Experience in techniques of Floor planning and top-level routing (matching, isolation/shielding). Experience with SAMSUNG, TSMC, IBM, GF and other technology processes. Good skills of Layout Physical Verification DRC/LVS/ANT/PAD/ESD.
Skilled in:
Synopsys Cosmos (SE, LE), Synopsys Custom Designer (SE, LE, SDL), Cadence Virtuoso LE, Design Compiler (DC), IC Compiler (ICC), ICWB, Hspice, VCS, Milkyway, Synopsys Hercules, Mentor Graphics Calibre, Spice, Verilog HDL.
Computer skills: Microsoft Windows, Linux, Microsoft Office
Scripting languages: Perl, Tcl